1. Field of the Invention
The present invention relates to a pattern forming method for use in the process of producing a semiconductor such as IC, in the production of a circuit board of liquid crystal, thermal head or the like or in other photofabrication processes, and also relates to a resist composition used therefor.
2. Background Art
The gate dimension of a semiconductor is becoming smaller year by year and according to the roadmap published in ITRS (The International Technology Roadmap for Semiconductor), the gate dimension and its dimensional variation in 3-sigma become 25 nm and 2.2 nm, respectively, in 2007. However, techniques known at present cannot achieve these dimensional controls.
In order to enhance the gate dimension uniformity, the dimensional uniformity of the resist pattern used at the gate processing must be enhanced, and enhancement of the dimensional uniformity have been heretofore made by various techniques.
The process of forming a resist pattern on a semiconductor substrate is generally a photolithography process comprising the following steps:
1. a photoresist solution is spin-coated on a semiconductor substrate (wafer),
2. the wafer is baked to remove the excess solvent contained in the coated photoresist layer,
3. the baked wafer is cooled to room temperature,
4. the photoresist layer is irradiated (exposed) with radiation though a mask to obtain a desired resist pattern,
5. the wafer is baked to make uniform the chemical reaction in the photoresist layer,
6. the baked wafer is cooled to room temperature,
7. the wafer is applied with a developer to remove the chemically changed photoresist layer (or chemically unchanged photoresist layer), and
8. the wafer is rinsed with pure water to remove the developer and then dried.
An attempt for enhancing the dimensional uniformity of the resist pattern is being made in each step such as coating, baking and development of the resist.
For example, it is studied to optimize the baking temperature, the temperature distribution of a hot plate on which the baking is performed, and the environment in which the hot plate is placed, or prevent re-adhesion of a volatile component from the resist onto the resist film at the baking.
As for the development step, it is studied to design the method of dropping a developer on the wafer, optimize the composition or temperature of the developer, or enhance the wettability of the resist film surface to the developer. Also, optimization of the concentration of the resist composition in the developer or optimization of the developing apparatus, particularly the shape of a nozzle for supplying a developer onto the wafer or the method of supplying the developer, is being studied.
As for the coating step, it is studied to enhance the dimensional uniformity by uniformly forming a resist film on a substrate. For example, in JP-A-7-320999 (the term “JP-A” as used herein means an “unexamined published Japanese patent application”), JP-A-10-223501, JP-A-2000-82647, JP-A-2000-150352, JP-A-2000-321458, JP-A-2003-136014, JP-A-2003-303757, JP-A-2005-128516, a method for forming a uniform coating film on a wafer is disclosed.
However, sufficiently high dimensional uniformity could not be achieved by these methods.